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Figure 1
The flange design of the camera housing, including the Timepix hybrid pixel detector in the centre (Supplementary Fig. S1). The tiled detector assembly holds four Timepix quads (512 × 512 pixels each). The dark grey top layers pointed out by the arrows represent the sensitive silicon layers of a pair of Timepix quads and the light grey slabs below represent the chip board. The gaps between the chips are necessary to accommodate the wire bonds to the readout boards.

Journal logoSTRUCTURAL
ISSN: 2059-7983
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