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Figure 1
Schematic of the pixel structure. Shown are the electronics integrated into each pixel within the PAD. Charge produced by the conversion of X-rays within the diode is integrated onto the capacitor in the input stage. Rapid imaging is accomplished by storing the integrated voltage level from successive images onto one of eight storage capacitors (C1–C8). Digital switching logic is used to select the desired capacitor. On readout, each capacitor is connected in succession to the output amplifier which is multiplexed to a buffer amplifier at the end of each pixel row. Also shown are various pixel control switches: IR, integrator reset; SE, store enable; RE, read enable; OE, output enable; OR, output reset.

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