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Figure 1
(a) Single readout port CCD showing horizontal clocking in the parallel registers and vertical clocking in the serial register. (b) A two-port readout architecture. Charge packets are shifted simultaneously, but in opposite directions from the parallel registers, into two serial registers. With a given read rate, this reduces full frame readout time by a factor of two. (c) A four-port readout architecture. Note that four full sets of analog and analog-to-digital converters must be used in parallel, significantly increasing the cost of the support electronics.

Journal logoJOURNAL OF
SYNCHROTRON
RADIATION
ISSN: 1600-5775
Volume 12| Part 5| August 2005| Pages 618-625
doi:10.1107/S0909049505022600
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