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Figure 1
Schematic view of the architecture of the PILATUS I chip (top) with a zoom to a single pixel (bottom). CS Amp = charge-sensitive amplifier; SR counter = shift-register counter. For explanations of other symbols see text. |
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Figure 1
Schematic view of the architecture of the PILATUS I chip (top) with a zoom to a single pixel (bottom). CS Amp = charge-sensitive amplifier; SR counter = shift-register counter. For explanations of other symbols see text. |