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Figure 10
Layout of the first mixed-mode pixel array prototype. This ASIC was manufactured using the TSMC 0.25 µm five-metal thick-oxide MiM process on non-epi substrate via MOSIS service. The ASIC consists of a 16 × 16 array of mixed-mode pixels and 16 on-chip 8-bit ADCs which were arranged in one-per-column format. This prototype was designed to give digital-only output, with the on-chip ADCs used to digitize the residual analog signal (see Fig. 9[link]) at the end of the integration period. Variations of the mixed-mode pixel were distributed inside the array. Die size is 3.6 mm × 3.7 mm with approximately 185000 transistors. Pixels are 150 µm square and consist of an integrator front-end, a comparator, 18-bit pseudo-random counter and reset/readout logic. On-chip ADCs used successive approximation architecture and occupied approximately 150 µm × 400 µm die area. Significant pixel area was consumed by the bump-bonding pad, which was required due to the special bump-bonding technique used for this prototype.

Journal logoJOURNAL OF
SYNCHROTRON
RADIATION
ISSN: 1600-5775
Volume 13| Part 2| March 2006| Pages 110-119
https://doi.org/10.1107/S0909049505028529
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