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Figure 5
Full integration cycle of the detector electronics. Trace 1 shows the output of the sample-and-hold (S/H) circuit. Traces 2 and 3 show the control pulses of the reset and S/H switches, respectively. Trace 4 represents the acquisition pulse sent to the ADC. The solid lines show a cycle with the S/H disabled (following permanently), so that we directly see the output of the integrating amplifier. The dashed lines show a cycle with the S/H enabled. The small step in the integrator output at the end of the reset period is due to charge injection from the parasitic capacitance of the FET switch S2 into the feedback capacitor.

Journal logoJOURNAL OF
SYNCHROTRON
RADIATION
ISSN: 1600-5775
Volume 15| Part 4| May 2008| Pages 355-362
doi:10.1107/S0909049508008509
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