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Figure 6
Detector readout scheme in step-scan mode. The dashed line shows schematically the output voltage of the integrating amplifier with periodic reset. The output of the sample-and-hold circuit (solid line) is `quasi-constant' owing to the S/H being set to hold for most of the integration time. The pixel dwell time tdwell, indicated by the gray boxes, is much longer than the detector integration time tint. The short sampling period of the S/H circuit (about 20 µs) introduces a negligible inaccuracy.

Journal logoJOURNAL OF
SYNCHROTRON
RADIATION
ISSN: 1600-5775
Volume 15| Part 4| May 2008| Pages 355-362
doi:10.1107/S0909049508008509
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