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Figure 1
The pixel comprises a front-end integrating amplifier stage with four selectable integration capacitors and a reset switch, an array of sample-and-hold capacitors that are used to store analog values, and a readout amplifier stage. The sample-and-hold capacitors, Cs0-s7, are uniformly 300 fF and are addressed in parallel across the detector so that each capacitor value represents a pixel in a stored frame. The feedback capacitors, Cf1-f4, have approximate values of 300 fF, 466 fF, 500 fF and 700 fF. An externally supplied reference voltage, Vref, defines the virtual voltage for the pixel input attached to the bump-bond. VrefBuf and Vbp are externally supplied reference voltages. All switches are fast CMOS switches designed to reduce charge injection (Koerner & Gruner, 2011BB9).

Journal logoJOURNAL OF
SYNCHROTRON
RADIATION
ISSN: 1600-5775
Volume 23| Part 2| March 2016| Pages 395-403
doi:10.1107/S1600577515022754
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