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Figure 7
Testing the isolation of bunch trains at CHESS was carried out by synchronizing successive front-end integration times with a synchrotron synchronization signal and imposing a variable delay, tdelay. The output of the integration stage was then captured on sampling capacitors (Cap 0–Cap 4). A `high' signal for each sampling capacitor represents the integration window of the respective capacitor in the conceptual timing diagram. By successively advancing tdelay, a sequence of integrations can be phased with bunch trains, mapping bunch train profiles with a time resolution limited only by the intrinsic time resolution of the detector (see Fig. 8[link]).

Journal logoJOURNAL OF
SYNCHROTRON
RADIATION
ISSN: 1600-5775
Volume 23| Part 2| March 2016| Pages 395-403
doi:10.1107/S1600577515022754
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