view article
Figure 1
Images of the VIPIC + sensor die. (a) After deposition of solder bumps onto the back of an ASIC. (b) After flip-chip bonding of VIPIC + sensor to the PCB. (c) VIPIC organization. The dashed line in the box on the right-hand side indicates the split between the different CMOS layers. The prototype is a matrix of 64 × 64 pixels, which are divided into 16 groups. Each group has one serializer and low-voltage differential signaling (LVDS) driver that allows outputting the data from the group.

Journal logoJOURNAL OF
SYNCHROTRON
RADIATION
ISSN: 1600-5775
Volume 23| Part 2| March 2016| Pages 404-409
https://doi.org/10.1107/S1600577516000114
Follow J. Synchrotron Rad.
Sign up for e-alerts
E-alerts
Follow J. Synchrotron Rad. on Twitter
Twitter
Follow us on facebook
Facebook
Sign up for RSS feeds
RSS